Utilizing GPU cores to process hundreds of floating point operations in parallel for embedded apps
July 17, 2012 by Tony DeYoung
Cameron Swen from AMD writes about heterogeneous compute parallel processing for embedded systems where extensive integer or floating point operations have to be performed as quickly as possible.
An example he gives is for radar signal interpretation:
“Radar interpretation has to carry out a large number of floating point operations to identify targets, movement, etc. Radar data can be collected much faster than it can be processed, making these computations the primary bottleneck. To improve performance, radar system designers must add more processors (or cores) or increase their clock speeds, both of which work in direct opposition to the need to make these systems smaller and consume less power to meet SWaP (Size, Weight and Power) and thermal management requirements. Taking this capability and integrating it onto a single piece of silicon with an x86 CPU, known as an APU (Accelerated Processing Unit), enables this type of acceleration in applications that may have previously used an ordinary CPU. To achieve these levels of performance they would have had to use either a very high performance CPU that consumed a lot of power, or added a DSP or FPGA to the system that added power, size and cost to the system. New solutions are now available that enable up to 46 gigaflops of single precision floating point performance while consuming less than 4.5W of power.”